The present invention relates generally to phase locked loop circuits, and more particularly to improvements in starting up and stabilizing phase locked loops.
Phase locked loops (PLLs) are often used in integrated circuit (IC) devices to synthesize a fast (high frequency) clock based upon a slower clock. A suitable example of this need is in the presence of noise sensitive environments. Since most of the electrical noise of a system is generated by the off chip clock, it is advantageous to use a slower, low noise clock in the system and use a PLL to multiply the clock frequency inside the chip product.
In a classical implementation, a PLL circuit (FIG. 1) includes a phase detector 10 at the input side of the circuit to receive the reference clock signal and the local clock signal at inputs 11 and 12, respectively. The phase detector compares the phases of the two signals and supplies either an "up" signal or a "down" signal as a digital control signal to a charge pump 13, depending on whether the local clock signal is lagging or leading the reference clock signal, respectively. The charge pump 13 generates an analog version of the control signal at its output 14, which is fed through a low-pass loop filter 15 to remove or substantially reduce the higher frequency components and clock jitter otherwise attributable to oscillation of the local clock about the lock point. The output of the loop filter 15 is applied as an analog control input to a voltage-controlled oscillator (VCO) 17. If the control signal that derives from the phase detector 10 is up, the output frequency of VCO 17 is increased by an amount sufficient to bring the phase-lagging local clock signal into alignment (synchronization) with the edge of the reference clock signal. On the other hand, if the control signal is down, the VCO output frequency is commensurately decreased to bring the phase-leading local clock signal back into alignment with the edge of the reference clock signal.
The time interval consumed for the PLL to lock in phase alignment onto the reference signal or other input signal is referred to as the "lock time" (or sometimes, as the "start time" or "start-up") of the PLL. In general, a considerable lock time--delay--is typically experienced with PLL circuits heretofore available. Indeed, it is not unusual for the lock time to run 60 to 70 milliseconds (msec) or more. In the prior art PLL circuit of FIG. 1, where local clock is synchronized with the reference clock, for example, the presence of clock jitter can be a significant factor in increasing the lock time.
A primary objective of the present invention is to reduce the lock time interval of the PLL to a manageable level. This is particularly desirable where the PLL is used in a system or subsystem that performs a control function, such as in a microcontroller unit or device. The desire is to achieve a fast lock time, of the order of microseconds (.mu.sec) rather than msecs. Existing semiconductor PLL chips generally exhibit a lock time which is so slow that chip start-up requires holding the chip in reset throughout the lock time interval.
One prior art technique which as been advanced as a possible solution to the problem of substantial lock time is to use a lock detect bit, which effectively instructs that nothing is to be done until the detect bit goes active. But among other problems that arise from this technique is the inability to detect a proper lock, so this has not provided an adequate solution.